Wafer Level Mask Tools

What is Wafer Level Mask Tools?

Artwork has developed several software tools to automate the layout of wafer-level masks. They are most commonly used for fan-in and fan-out redistribution while building packages directly on a wafer. These tools greatly reduce the time required for wafer mask layout and reduce errors generated by a more manual approach.

GDS-SR - Step and Repeat

GDS-SR is a very powerful tool for removing one or more data through a wafer. Includes support for eliminating or replacing individual devices, producing SINF output, and delivering individual array or reticle input.

HExtract - Clipping and knockout

Hextract is a boolean that holds the matrix devices along the edge of the wafer to a perfectly round boundary. It can be directed to maintain or exclude small polygons that cross the border, depending on what the process requirements of each layer require.

WLayGen - Wafer Map Layout Generator and Shooting Map

WLayGen reads several different wafer map formats and produces a GDSII-format layout that is viewed in Qckvu3. You can also read the parameters of the reticle shot map provided by a foundry and produce a layout from that data. By overlaying the take map and wafer map data, the user can determine the exact location of each data on the wafer and use it as a model for the redistribution mask.

GDSFilt - GDSII Merge /Extraction Utility

GDSFILT is an advanced GDSII utility that can merge multiple GDSII files, replace one cell with another, and extract individual layers from a GDSII layout. It is used to insert special features into a wafer mask or to separate a drawing into individual layers.

LWDRC - RDC long live

If the RDL circuit is customer-designed (COTS), the packaging mask designer usually needs to verify that all line widths, ranges, and enclosures meet design rules. Lightweight CKD does this quickly and easily and costs 20X less than a full DRC used for integrated circuits.

Intelligent matrix coordinate extraction

Smart Die scans a chip and extracts the coordinates and sizes of the pad openings. Generally, this is the first step in the rdl drive cell design in tools such as Cadence APD/SIP.

StepVu - Step map viewer and Wafer

StepVu reads the ASML slider files or the SINF wafer map files and converts them to GDSII for display and measurement. This is very useful for the mask designer when dealing with these wafer casting input types.

WaferDoc / CellDoc - Automated documentation generators

These AutoCAD-based plug-ins help speed up documentation of wafer masks and drive cell design.

System requirements:

CPU: 1.8 GHz dual core processor

RAM: 2 GB

HDD / SSD: 50 GB of free space on the main drive

Operating system: Microsoft Windows 8 32-bit, Microsoft Windows 7 32-bit and Microsoft Windows Vista 32-bit

Resolution: 1024×768